Required Specifications: PC: should be synchronous block which have 64-bit input and 64-bit output. Instruction memory: should be synchronous block with PC; both have the same clock signal. Read address input is 16-bit wide and the instruction memory output must be 32 bits. Add unit: must be combinational circuit with 2 64-bit inputs, one of the input is 4. Constraints 1- Develop the Add unit without using any of IP catalog cores. 2- Initialize the first 5 locations of instruction memory by storing instruction codes in memory coefficient (COE) file. 3- Read address of the instruction memory must be connected to 16 least significant bits of PC. Requirements: I. Hard copy of your report and its pdf. file containing the following: 1. Modified block diagram, showing the bits and additional connections 2. What are the objectives 3. Elaboration on Verilog or VHDL implementation 4. Synthesis results; along with RTL view snap shot 5. Elaboration on test bench: e.g. how many instructions